Point contact array, not circuit, and electronic circuit comprising the same

ABSTRACT

There are provided a point contact array, in which a plurality of point contacts are arranged, each point contact electrically and reversibly controlling conductance between electrodes and being applicable to an arithmetic circuit, a logic circuit, and a memory device, a NOT circuit, and an electronic circuit using the same.  
     A circuit includes a plurality of point contacts each composed of a first electrode made of a compound conductive material having ionic conductivity and electronic conductivity and a second electrode made of a conductive substance. The conductance of each point contact is controlled to realize the circuit. Ag 2 S, Ag 2 Se, Cu 2 S, or Cu 2 Se is preferably used as the compound conductive material. When a semiconductor or insulator material is interposed between the electrodes, a crystal or an amorphous material of GeS x , GeSe x , GeTe x , or WO x  (0&lt;x&lt;100) is preferably used as the semiconductor or insulator material.  
     A NOT circuit is realized using a device which includes an atomic switch serving as a two-terminal device, the device including a first electrode made of a compound conductive material having ionic conductivity and electronic conductivity and a second electrode made of a conductive substance, and capable of controlling conductance between the electrodes.

TECHNICAL FIELD

[0001] The present invention relates to a point contact array comprisinga plurality of devices in each of which a point contact is formed ordisconnected between electrodes facing each other to controlconductance, a NOT circuit, and an electronic circuit using the same,and more particularly to a NOT circuit comprising an electronic device(an atomic switch which will be described below) in which a pointcontact is formed or disconnected between electrodes facing each otherto control conductance, and an electronic circuit using the same.

BACKGROUND ART

[0002] As related arts [1], methods for forming a point contact tocontrol conductance are disclosed by, for example, J. K. Gimzewski andR. Moller: Phys. Rev. B36, p1284, 1987, J. L. Costa-Kramer, N. Garcia,P. Garcia-Mochales, P. A. Serena, M. I. Marques, and A. Corrcia: Phys.Rev. B55, p5416, 1997, and H. Ohnishi, Y. Kondo, and K. Takayanagi:Nature, Vol. 395, p780, 1998.

[0003] Each of these methods requires a piezo device in order to formand control each point contact. In other words, a metallic probeequipped with the piezo device is positioned with respect to an oppositeelectrode with high precision by driving the piezo device, thus forminga point contact between the probe and the opposite electrode. The statethereof is controlled.

[0004] In addition to these arts, as a related art [2], a method forcontrolling conductance of each point contact, the method using organicmolecules is disclosed by C. P. Collier et al.: Science, Vol. 285, p391,1999.

[0005] According to this method, the conductivity of rotaxane moleculesof one molecule thickness sandwiched by electrodes facing each other ischanged by applying high voltage between the electrodes. In other words,the rotaxane molecules, sandwiched between the electrodes, initiallyexhibit the conductivity. When a predetermined or higher voltage of acertain polarity is applied, the molecules are oxidized to reduce theconductivity, so that the electrodes are isolated from each other.

[0006] [3] Hitherto, it is known that an AND circuit and an OR circuitcan be formed using a diode serving as a two-terminal device.

[0007] On the other hand, it is also well-known that a NOT circuitcannot be formed using only the diode. In other words, the NOT circuitcannot be formed using only the conventional two-terminal devices.Accordingly, the formation of the NOT circuit requires a transistorserving as a three-terminal device.

[0008] All of logic circuits can be constructed using the combination ofthe AND circuit, the OR circuit, and the NOT circuit. In other words, athree-terminal circuit is indispensable to the formation of an arbitrarylogic circuit. This fact is described in detail in, for example, “NYUMONELECTRONICS KOHZA (Library of Introduction to Electronics) DigitalCircuit”, Vol. 2, pages 1 to 7, published by Nikkan Kogyo Shinbun Co.,Ltd. (I).

[0009] Nowadays as the integration of silicon devices is approaching itslimit, new nanometer-sized devices such as molecular devices are beingdeveloped. For example, the result of the experiment of a transistorusing a carbon nanotube is described in Nature, Vol. 393, pages 49 to50, 1998 (II).

DISCLOSURE OF INVENTION

[0010] According to the method of the foregoing related arts [1],however, one point contact needs at least one piezo device and acomplicated control circuit for driving the device. It is very difficultto integrate these components.

[0011] According to the method of the foregoing related art [2], sincetemporarily oxide molecules are reduced and the conductivity cannot berestored, the application is remarkably restricted. Further, for [3],the foregoing three-terminal circuit becomes a factor to inhibitminiaturization.

[0012] For example, according to the method of the foregoing document(II), a structure such as a gate other than the carbon nanotube isformed by applying an existing process for manufacturing a semiconductordevice. Accordingly, the size of the entire transistor is not sodifferent from that of the conventional transistor. In other words,actually, the development of nanometer-sized devices still remains inthe stage of demonstrations of the fundamental principle.

[0013] In consideration of the above situations, a first object of thepresent invention is to provide a point contact array including aplurality of point contacts each of which electrically and reversiblycontrols conductance between electrodes and each of which is applicableto an arithmetic circuit, a logic circuit, and a memory device.

[0014] A second object of the present invention is to provide a NOTcircuit including a nanometer-sized electronic device and an electroniccircuit using the same.

[0015] To accomplish the above objects, according to the presentinvention,

[0016] [1] there is provided a point contact array including a pluralityof electronic devices, each of which includes a first electrode made ofa compound conductive material having ionic conductivity and electronicconductivity and a second electrode made of a conductive substance andeach of which can control conductance between the electrodes.

[0017] [2] In the point contact array described in [1], preferably, thecompound conductive material having mobile ions (M ion: M denotes ametallic atom) is formed on a source of the mobile ions (M).

[0018] [3] In the point contact array described in [1] or [2],preferably, the compound conductive material is Ag₂S, Ag₂Se, Cu₂S, orCu₂Se.

[0019] [4] In the point contact array described in [1], [2], or [3],preferably, the mobile ions, contained in the compound conductivematerial, form a bridge between the first and second electrodes tochange the conductance between the electrodes.

[0020] [5] In the point contact array described in [1], [2], or [3],preferably, a semiconductor or insulator material, which can dissolveions and which exhibits electronic conductivity and ionic conductivitydue to the dissolution of ions, is arranged between the first and secondelectrodes, and mobile ions contained in the compound conductivematerial enter the semiconductor or insulator material to change theconductance of the semiconductor or insulator.

[0021] [6] In the point contact array described in [5], preferably, thesemiconductor or insulator material is a crystal or an amorphousmaterial of GeS_(x), GeSe_(x), GeTe_(x), or WO_(x) (0<x<100).

[0022] [7] In the point contact array described in [1], [2], [3], [4],[5], or [6], preferably, a metallic wire, of which at least one part iscovered with the compound conductive material, functions as the firstelectrode, a metallic wire functions as the second electrode, aplurality of metallic wires functioning as at least one of theelectrodes exist, and a point contact is arranged at each intersectionof the metallic wires.

[0023] [8] In the point contact array described in [1], [2], [3], [4],[5], [6], or [7], preferably, the conductance of each point contact isquantized.

[0024] [9] The point contact array described in [8] may function as amultiple recording memory device in which the quantized conductance ofeach point contact is used as a recording state.

[0025] [10] In the point contact array described in [8], preferably, thequantized conductance of each point contact is used as an input signal,and the potentials of the respective electrodes are controlled toperform addition or subtraction of the input signals.

[0026] [11] The point contact array described in [1], [2], [3], [4],[5], [6], or [7] may function as a logic circuit in which a potential atone end of each point contact is used as an input signal.

[0027] [12] There is provided a NOT circuit including only two-terminaldevices.

[0028] [13] There is provided a NOT circuit including an atomic switchserving as a two-terminal device.

[0029] [14] In the NOT circuit described in [13], preferably, the atomicswitch includes a device, which includes a first electrode made of acompound conductive material having ionic conductivity and electronicconductivity and a second electrode made of a conductive substance andwhich can control conductance between the first and second electrodes.

[0030] [15] In the NOT circuit described in [14], preferably, thecompound conductive material is Ag₂S, Ag₂Se, Cu₂S, or Cu₂Se.

[0031] [16] The NOT circuit described in [14] or [15] may include aresistor and a capacitor, each of which serves as a two-terminal device,in addition to the atomic switch.

[0032] [17] The NOT circuit described in [16] may include a diode inaddition to the resistor and the capacitor.

[0033] [18] In the NOT circuit described in [16], preferably, a voltageto be applied to the atomic switch is controlled through the capacitorto control the conductance of the atomic switch.

[0034] [19] There is provided an electronic circuit including acombination of the NOT circuit described in any one of [13] to [18], andan AND circuit and an OR circuit, each of which includes the atomicswitch.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035]FIG. 1 is a schematic perspective view showing a point contactarray, in which a plurality of point contacts are arranged, according tothe present invention.

[0036]FIG. 2 is a schematic view showing a point contact arrayconstituting a multiple storage memory according to the presentinvention.

[0037]FIG. 3 shows the result of reading of the multiple storage memoryaccording to a first embodiment of the present invention.

[0038]FIG. 4 shows the result of an arithmetic operation by an addingcircuit comprising a point contact array according to a secondembodiment of the present invention.

[0039]FIG. 5 shows the result of an arithmetic operation by asubtracting circuit comprising a point contact array according to athird embodiment of the present invention.

[0040]FIG. 6 is a schematic diagram of an OR gate comprising a pointcontact array according to a fourth embodiment of the present invention.

[0041]FIG. 7 shows the results of the operation of an OR gate comprisinga point contact array according to the fourth embodiment of the presentinvention.

[0042]FIG. 8 is an equivalent circuit diagram of a point contact arraylogic circuit according to the fourth embodiment of the presentinvention.

[0043]FIG. 9 is a schematic diagram of an AND gate comprising a pointcontact array according to a fifth embodiment of the present invention.

[0044]FIG. 10 shows the results of the operation of the AND gatecomprising the point contact array according to the fifth embodiment ofthe present invention.

[0045]FIG. 11 is a view showing a method for forming a point contactarray according to a sixth embodiment of the present invention.

[0046]FIG. 12 is a schematic view of a point contact array according toa seventh embodiment of the present invention, the point contact arraycontrolling the conductivities of semiconductors.

[0047]FIG. 13 is a schematic view of a point contact array according toan eighth embodiment of the present invention, the point contact arrayhaving electrodes partially covered with a compound conductor.

[0048]FIG. 14 is a schematic diagram of a NOT circuit according to aninth embodiment of the present invention.

[0049]FIG. 15 includes graphs showing a principle of the operation ofthe NOT circuit according to the ninth embodiment of the presentinvention.

[0050]FIG. 16 is a schematic diagram of a NOT circuit according to atenth embodiment of the present invention.

[0051]FIG. 17 includes graphs showing a principle of the operation ofthe NOT circuit according to the tenth embodiment of the presentinvention.

[0052]FIG. 18 is a schematic diagram of a NOT circuit according to aneleventh embodiment of the present invention.

[0053]FIG. 19 includes graphs showing a principle of the operation ofthe NOT circuit according to the eleventh embodiment of the presentinvention.

[0054]FIG. 20 is a schematic diagram of a NOT circuit according to atwelfth embodiment of the present invention.

[0055]FIG. 21 is a schematic diagram of a one-digit binary adderaccording to a thirteenth embodiment of the present invention.

[0056]FIG. 22 is a diagram showing logical symbols of the one-digitbinary adder according to the thirteenth embodiment of the presentinvention.

[0057]FIG. 23 is a diagram showing a truth table of the one-digit binaryadder according to the thirteenth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0058] Embodiments of the present invention will be described in detailhereinbelow with reference to the drawings.

[0059]FIG. 1 is a schematic perspective view showing a point contactarray, in which a plurality of point contacts are arranged, according tothe present invention.

[0060] As shown in FIG. 1, point contacts (bridges) 6 and 7 eachcomprising mobile ions (atoms) 5 are formed at the intersections of ametallic wire (first electrode) 2 and metallic wires (second electrodes)3 and 4, the metallic wire 2 being covered with an electronic/ionicmixed conductor 1. These components are arranged on an insulatingsubstrate 8 and are then fixed thereto using an insulating material (notshown).

[0061] When a semiconductor or insulator material is interposed betweenthe first and second electrodes, mobile ions are dissolved into thesemiconductor or insulator to change the conductance of thesemiconductor.

[0062] Consequently, the conductance between the electrodes is changed.The amount of change depends on the amount of the mobile ions dissolvedin the semiconductor or insulator material.

[0063] For the sake of simplification, FIG. 1 shows the point contactarray comprising the one metallic wire (first electrode) 2, covered withthe electronic/ionic mixed conductor 1, and the two metallic wires(second electrodes) 3 and 4. The number of point contacts is obtained bymultiplying the number of metallic wires each constituting theelectrode. In this case, 2×1, namely, two point contacts are formed.When the number of metallic wires constituting the first and secondelectrodes is increased, a point contact array having n×n point contactscan be formed.

[0064] According to the present invention, a voltage is applied betweenthe first electrode 2 and the second electrodes 3 and 4, resulting inthe formation or disappearance of the bridges 6 and 7 comprising ionatoms. Thus, the conductance of each point contact formed between theelectrodes is controlled. Specifically, when a proper negative voltageis applied to the second electrodes 3 and 4 with respect to the firstelectrode 2, mobile ions (atoms) in the electronic/ionic mixedconductive material are precipitated due to effects of voltage andcurrent, resulting in the formation of the bridges 6 and 7 between theelectrodes. Consequently, each conductance between the electrodes isincreased. On the other hand, when a proper positive voltage is appliedto the second electrodes 3 and 4, the mobile ions (atoms) return to theelectronic/ionic mixed conductive material, resulting in thedisappearance of the bridges 6 and 7. In other words, the conductance isreduced.

[0065] As mentioned above, a voltage applied to each metallic wire isindependently controlled, so that a voltage applied to the point contactformed at each of the intersections of the first electrode 2 and thesecond electrodes 3 and 4 can be independently controlled. In otherwords, the conductance of the point contact at each intersection can beindependently controlled.

[0066] In this manner, an electronic device such as a memory device oran arithmetic device comprising a point contact array and an electriccircuit comprising the electronic devices can be formed.

[0067] Embodiments using a first electrode comprising anelectronic/ionic mixed conductive material of Ag₂S and an Ag which is asource of mobile ions of Ag and second electrodes comprising Pt will nowbe described hereinbelow. It is needless to say that the similar resultscan be obtained using other materials.

[0068] When there are about ten atoms of Ag, each bridge can besufficiently formed. On the basis of the measurement result, oncondition that a voltage is 100 mV and initial interelectrode resistanceis 100 kΩ, the time required to derive ten Ag atoms from Ag₂S serving asthe electronic/ionic mixed conductor, namely, the time required to forma bridge is estimated to be tens of nanoseconds at most. An electricpower required to form the bridge is on the order of nanowatts, namely,the power is small. Accordingly, the application of the presentinvention realizes the construction of a high-speed device with lowpower consumption.

[0069] A first embodiment of the present invention will now bedescribed.

[0070]FIG. 2 shows a schematic view of a point contact array accordingto the present invention, the point contact array being applied to amultiple memory device.

[0071] For the sake of simplification, a sample comprising two pointcontacts is used in a manner similar to FIG. 1. In this case, Ag₂S isused as an electronic/ionic mixed conductive material 11 functioning asa first electrode and an Ag wire is used as a metallic wire 10. Pt wiresare used as metallic wires 13 and 14 each functioning as a secondelectrode. The first electrode is grounded and voltages V1 and V2 areindependently applied to the second electrodes 13 and 14, respectively.When negative voltages are used as V1 and V2, Ag atoms 12 contained inthe electronic/ionic mixed conductive material 11 are precipitated toform bridges 15 and 16. When positive voltages are used as V1 and V2,the Ag atoms 12 in the bridges 15 and 16 return to the electronic/ionicmixed conductive material 11, resulting in the disappearance of thebridges 15 and 16. Japanese Patent Application No. 2000-265344, by theinventors of the present application, proposes the detailed mechanism.

[0072] According to the present invention, the use of a plurality ofpoint contacts realizes a new function, which will be describedhereinbelow.

[0073] According to the present embodiment, pulse voltages are appliedto control the conductance of each point contact. In other words, inorder to increase the conductance, a voltage of 50 mV is applied for 5ms. In order to reduce the conductance, a voltage of −50 mV is appliedfor 5 ms. Thus, transition in the quantized conductance of each pointcontact is realized. In other words, the transition corresponds to thewriting operation of the memory.

[0074] In order to read a recording state, V1 and V2 are set to 10 mV sothat the recorded conductance is not changed by the reading operation.In this situation, current I₁ and I₂ flowing through the metallic wires13 and 14, each functioning as the second electrode of the pointcontact, are measured. FIG. 3 shows the result.

[0075] Referring to FIG. 3, I₁ is shown by a thin solid line and I₂ isshown by a thick solid line. The point contact 15 or 16 is subjected tothe writing operation every second. The recording state is read outafter each writing operation. The ordinate axis on the left denotes acurrent actually measured. The ordinate axis on the right denotesquantized conductance corresponding thereto. The conductance is obtainedby dividing the measured current by the applied voltage (10 mV).

[0076] It is understood from the graph that the conductance of eachpoint contact is quantized. In other words, when it is assumed that N₁denotes the quantum number of the quantized conductance of a first pointcontact serving as the bridge 15 and N₂ denotes the quantum number ofthe quantized conductance of a second point contact serving as thebridge 16, N₁=0 to 3 and N₂=0 to 3, namely, 16 recording states arerealized in total.

[0077] According to the present embodiment, four quantized states of N=0to 3 are used. If a state having a larger quantum number is used, therecording density can be increased. It is needless to say that therecording density can also be increased by increasing the number ofpoint contacts.

[0078] A second embodiment of the present invention will now bedescribed.

[0079] First, an example in which an adding circuit is realized with theconfiguration shown in the first embodiment will be described.

[0080] According to the present invention, inputs denote the quantumnumbers N₁ and N₂ of the quantized conductance of the point contactsserving as the bridges 15 and 16. The input operation is performed bycontrolling the voltages V1 and V2 to set each of N₁ and N₂ to a desiredvalue. V1 and V2 are set to a reading voltage, for example, 10 mV and acurrent I_(out) flowing from the first electrode 10 to a groundpotential is measured, thus obtaining the result of an arithmeticoperation.

[0081]FIG. 4 shows the result of the arithmetic operation according tothe second embodiment of the present invention. Below a graph, theinputted N₁ and N₂ and measured N_(out) are shown so as to correspond tothe abscissa axis of the graph. It is found that the obtained currentI_(out) has quantized conductance corresponding to (N₁+N₂). In otherwords, the addition is correctly performed. According to the presentembodiment, 16 addition results corresponding to N₁=0 to 3 and N₂=0 to 3are shown in the same way as the first embodiment. Larger quantumnumbers can also be used. For the number of point contacts used, namely,the number of inputs, three or more inputs can also be used.

[0082] A third embodiment of the present invention will now bedescribed.

[0083] The configuration shown in the first embodiment can also beapplied to a subtracting circuit. Inputs are controlled by the samemethod described in the second embodiment. Upon subtraction, voltages,which have the same absolute value and whose polarities are opposite toeach other, can be used as V1 and V2. For example, when V1 is set to 10mV and V2 is set to −10 mV, the current I_(out) corresponding toquantized conductance, which corresponds to (N₁−N₂) , flows from thefirst electrode to the ground potential. At that time, when the currentflows in the direction from the first electrode to the ground potential,the result of the arithmetic operation indicates a positive value. Whenthe current flows in the direction from the ground potential to thefirst electrode, the result of the arithmetic operation indicates anegative value.

[0084]FIG. 5 shows the result of the arithmetic operation according tothe third embodiment.

[0085] The arithmetic operation of (N₁−N₂) is correctly performed.Further, if three or more point contacts are used, an arithmeticoperation of (N₁+N₂−N₃) can be performed at a time. In this case, forexample, on condition that V1 and V2 are set to 10 mV and V3 is set to−10 mV, the arithmetic operation can be performed.

[0086] A fourth embodiment of the present invention will now bedescribed.

[0087] According to the present embodiment, a logic circuit isconstructed using the point contacts according to the present invention.For the configuration of the logic circuit, in contrast to the first tothird embodiments, the transition in the quantized conductance of eachpoint contact is not used. In other words, the point contact is used asan on-off switching device. Typically, a resistance in the ON state isequal to or less than 1 kΩ and a resistance in the OFF state is equal toor more than 100 kΩ.

[0088]FIG. 6 is a schematic diagram of an OR gate formed using the pointcontacts according to the present invention.

[0089] Ag wires 21 and 22 are covered with Ag₂S 23 and 24, respectively,thus forming first electrodes. Ag bridges 25 and 26, formed on the Ag₂S23 and 24, face a Pt electrode 20 serving as a second electrode, thusforming point contacts. One end of the Pt electrode 20 is connected to areference voltage V_(S) through a resistance 27 (10 kΩ in the presentembodiment) and the other end functions as an output terminal togenerate an output voltage V_(out). Input voltage V1 and V2 are appliedto the Ag wires 21 and 22, resulting in the formation or disappearanceof the bridges 25 and 26. Thus, each point contact functions as anon-off switching device.

[0090]FIG. 7 shows the results of the operation. According to thepresent embodiment, the inputs, namely, V1 and V2 are changed everysecond to measure the output V_(out).

[0091] In a two-input OR gate, for binary low-level and high-levelinputs, if either input indicates a high level, an output must go to ahigh level.

[0092] The OR gate is operated using 0 V (the reference potential Vsalso has the same value) as a low-level input and 200 mV as a high-levelinput. FIG. 7(a) shows the result of this case.

[0093] When either one of the two inputs V1 and V2 is 200 mV, the outputV_(out) substantially indicates 200 mV. The normal operation is foundfrom the graph. When a high-level voltage is increased to 500 mV, thesimilar result (FIG. 7(b)) is obtained.

[0094]FIG. 8 is an equivalent circuit diagram of the present logiccircuit.

[0095] The reference voltage Vs and the input voltages V1 and V2 causethe formation or disappearance of the bridges 25 and 26 (FIG. 6),resulting in a change in the resistance of each of resistors R1 and R2(resistances of the point contacts formed by the bridges). Althoughthere is a small resistance R12 (about several ohms to tens of ohms)between two point contacts on the electrode 20 (FIG. 6), the resistanceis negligible as compared to R0 (10 kΩ), and R1 and R2 (1 kΩ to 1 MΩ).

[0096] First, when both of V1 and V2 are 0 V, all of the three voltagesconnected to the system indicate 0 V. Therefore, the output V_(out)necessarily indicates 0 V. Subsequently, when V1 is 0 V and V2 is 200 mV(500 mV), the bridge 25 (FIG. 6) grows and the resistance of theresistor R2 decreases. Typically, the resistance is equal to or lessthan 1 kΩ.

[0097] Consequently, since the resistance of R2 is an order or more ofmagnitude smaller than that of R0, V2′ indicates about 200 mV (500 mV).At this time, since V1′ also indicates about 200 mV (500 mV), a voltagewhereby a bridge disappears is applied to the bridge 26 (FIG. 6), sothat R1 indicates a large value of 1 MΩ or higher. Consequently, when V1is 0 V, R0, R1>>R2. Accordingly, V1′ indicates about 200 mV (500 mV)that is equivalent to V2′. Thus, the output indicates 200 mV (500 mV).To be precise, the growth of the bridge 25 and the disconnection of thebridge 26 simultaneously occur, thus causing the above-described result.

[0098] In a case where V1 is 200 mV (500 mV) and V2 is 0 V, the similarexplanation can be applied to the case. When both of V1 and V2 are 200mV (500 mV), both of the bridges 25 and 26 grow. Consequently, thevoltage of V1 and V2, namely, 200 mV (500 mV) is generated.

[0099] A fifth embodiment of the present invention will now bedescribed.

[0100] According to the present embodiment, the configuration of an ANDgate will be described with reference to FIG. 9.

[0101] According to the present embodiment, one end of an Ag wire 30,covered with an Ag₂S thin film 31, is connected to a reference voltageVs through a resistor 37. The other end is an output terminal. Bridges33 and 34, formed by precipitation of Ag atoms serving as mobile ions,are formed so as to face two Pt electrodes 35 and 36, respectively.Input voltages V1 and V2 are applied to the two Pt electrodes 35 and 36.In FIG. 9, reference numeral 32 denotes an Ag ion in the Ag₂S thin film31.

[0102]FIG. 10 shows the results of the arithmetic operation of the ANDgate. In the two-input AND gate, when both of the two inputs are at ahigh level, an output V_(out) goes to a high level.

[0103]FIG. 10(a) shows the result of the operation on condition that thehigh level is set to 200 mV. In this instance, a reference voltage isalso set to 200 mV.

[0104]FIG. 10(b) shows the result of the operation on condition that thehigh level is set to 500 mV. In this instance, the reference voltage is500 mV.

[0105] Referring to FIG. 10, when the high level is set to 200 mV, V1 is0 V, and V2 is 200 mV, the output V_(out) indicates a partial value(about 50 mV). However, in the other cases, the output indicates 0 V asthe low level or 200 mV as the high level. When the high level is set to500 mV, the normal operation is performed in all of input patterns. Inthe case of the operation using 200 mV, when a critical voltage todetermine low-high levels is set to 100 mV, no problem occurs. The causewill be described below.

[0106] The principle of the operation of the AND gate will be describedagain with reference to FIG. 8. According to the present embodiment, thereference voltage Vs is at the high level (200 or 500 mV). First, whenboth of V1 and V2 are 0 V, both of the bridges 33 and 34 (FIG. 9) grow.Thus, the resistance of each of the resistors R1 and R2 is typicallyequal to or less than 1 kΩ. In other words, the input voltages at thelow level are connected to the output terminal through resistances whichare one order or more of magnitude smaller than the resistance R0 (10kΩ). Accordingly, the output V_(out) indicates 0 V. Subsequently, whenV1 is 0 V and V2 is 200 mV (500 mV), the bridge 33 (FIG. 9) alone grows.

[0107] On the other hand, in the bridge 34, the voltage V2′ is smallerthan 200 mV (500 mV) due to the voltage V1. In other words, the voltageof a polarity, which allows the bridge to disappear, is applied to thebridge 34, resulting in the disappearance of the bridge 34. Theresistance of R2 is increased to about 1 MΩ. In this instance, when apotential difference between V2′ and V2 is small, the bridge disappearsinsufficiently. Therefore, the resistance of R2 is not increased enough.Accordingly, the above-mentioned partial output may be generated.However, when a high-level voltage is set to 500 mV, the potentialdifference between V2′ and V2 is increased enough. Thus, the completelynormal operation is realized.

[0108] The same description applies in the case where V1 is 200 mV (500mV) and V2 is 0 V. Since the characteristics of the bridges 33 and 34each constituting the point contact are slightly different from eachother, a normal output is obtained in the case where an operatingvoltage is 200 mV. Finally, when both of V1 and V2 are 200 mV (500 mV),the formation or disappearance of the bridges 33 and 34 does not occur.Since all of voltages are 200 mV (500 mV), an output voltage alsoindicates 200 mV (500 mV).

[0109] The logic circuits using the point contacts have been described.According to the foregoing embodiments, the two-input logic circuitshave been explained. When three or more point contacts according to thepresent invention are used, a logic circuit having three or more inputscan be formed on the basis of the above-mentioned principle ofoperation.

[0110] A sixth embodiment according to the present invention will now bedescribed.

[0111] A method for forming a point contact array will be described.

[0112]FIG. 11 is a diagram showing the method for forming a pointcontact array according to the sixth embodiment of the presentinvention.

[0113] As shown in FIG. 11, Ag wires 41 and 42 are formed on aninsulating substrate 40. The surfaces of the Ag wires are sulfurized toform Ag₂S films 43 and 44. Pt wires 45 and 46 are disposed thereon.Thus, an essential part of the point contact array is completed. It isimportant that bridges 47 and 48 comprising Ag atoms are formed at theintersections of the Ag wires 41 and 42 and the Pt wires 45 and 46, theAg wires 41 and 42 being covered with the Ag₂S films 43 and 44,respectively.

[0114] According to the present invention, therefore, when the Pt wires45 and 46 are arranged, a voltage is applied between the Pt wires 45 and46 and the Ag wires 41 and 42 to precipitate Ag on the Ag₂S film 43 and44, resulting in the formation of the bridges 47 and 48. Consequently,when the Pt wires 45 and 46 are arranged using, for example, a wiringsystem or the like, the present invention can be realized.

[0115] The bridge can be previously formed at each intersection byevaporation of Ag through a mask. Alternatively, electron beams can beirradiated on each Ag wire covered with the Ag₂S film to precipitate Agatoms. It is important that Ag exists between Ag₂S functioning as afirst electrode and Pt functioning as a second electrode.

[0116] Furthermore, Pt wires can be previously formed on anothersubstrate and be then adhered to the substrate having the Ag wirescovered with the Ag₂S films.

[0117] A seventh embodiment of the present invention will now bedescribed.

[0118] A method for forming another point contact array and thestructure thereof will be described.

[0119]FIG. 12 is a schematic view of a point contact array according tothe seventh embodiment of the present invention, the point contact arraycontrolling the conductivity of each semiconductor.

[0120] Referring to FIG. 12, Ag wires 51 and 52, respectively coveredwith Ag₂S films 53 and 54, are formed on an insulating substrate 50.Further, semiconductors or insulators 57, 58, 59, and 60, which candissolve Ag atoms, are formed only at the intersections of the Ag wires51 and 52 and the Pt wires 55 and 56. In FIG. 12, an insulating materialcovering these components are not shown. All of the components shown inthe diagram are embedded in a device.

[0121] In this case, according to the same principle as that describedabove, Ag ions move from the Ag₂S films 53 and 54. The moving Ag ionsare dissolved into the semiconductors or insulators 57, 58, 59, and 60to change the conductivity of each semiconductor or insulator. Thus, thesimilar effects as those in the above-mentioned embodiments can berealized. In this case, since a space where the formation ordisappearance of the bridges is not needed in the device, thesecomponents can be easily embedded in an insulating member.

[0122] When Ag thin films are previously formed in place of thesemiconductors or insulators, the same structure as that described inthe sixth embodiment is obtained. In this case, Ag atoms contained inthe Ag thin films enter the Ag₂S films, resulting in the disappearanceof the thin film.

[0123] According to the present invention, crystals or amorphousmaterials of GeS_(x), GeSe_(x), GeTe_(x), or WO_(x) (0<x<100) are usedas the semiconductors or insulators which can dissolve the Ag ions.

[0124] An eighth embodiment of the present invention will now bedescribed.

[0125]FIG. 13 shows an embodiment in which a part of each metallic wireserving as a first electrode is covered with an electronic/ionic mixedconductor. According to the present embodiment, it is enough to formpoint contacts, each comprising “a metal serving as a first electrode,an electronic/ionic mixed conductor, a bridge or a semiconductor, and ametal serving as a second electrode”, at the intersections of themetallic wire functioning as the first electrode and metallic wires eachfunctioning as the second electrode.

[0126] Therefore, as shown in FIG. 13, when electronic/ionic mixedconductors 73 and 74 are formed only in the vicinity of theintersections of a metallic wire 70 functioning as a first electrode andmetallic wires 71 and 72 each functioning as a second electrode, a pointcontact (bridge) 75 can be formed between the electronic/ionic mixedconductor 73 and the metallic wire 71 and a point contact (bridge) 76can be formed between the electronic/ionic mixed conductor 74 and themetallic wire 72.

[0127] Furthermore, for the metal serving as the first electrode, eachpart which is in contact with the electronic/ionic mixed conductor canbe different from a material of the wire between the point contacts.According to the present embodiment, for example, Ag wires 79 and 80 areused as parts which are in contact with electronic/ionic mixedconductors (Ag₂S) 77 and 78, respectively. Tungsten wires are used asother parts 81 to 83. For the material of each part to be in contactwith the electronic/ionic mixed conductor, it is necessary that eachpart comprise the same element as the mobile ions in theelectronic/ionic mixed conductor. According to the present embodiment,therefore, since Ag₂S is used as the electronic/ionic mixed conductor,Ag is used as a material for the part which is in contact therewith.

[0128] A NOT circuit according to another embodiment of the presentinvention and an electronic circuit using the same will now be describedin detail hereinbelow.

[0129]FIG. 14 is a schematic diagram of a NOT circuit according to aninth embodiment of the present invention.

[0130] As shown in the diagram, a first electrode 102 serving as anelectronic/ionic mixed conductor is formed on a conductive substance101. A potential difference between the first electrode 102 and a secondelectrode 103 is controlled, thus controlling so that mobile ions(atoms) 104 in the electronic/ionic mixed conductor are precipitated asmetallic atoms on the surface of the first electrode 102, alternatively,the precipitated metallic atoms are dissolved as mobile ions (atoms)into the first electrode 102. In other words, when a proper negativevoltage is applied to the second electrode 103 with respect to the firstelectrode 102, the mobile ions (atoms) 104 in the electronic/ionic mixedconductive material is precipitated due to the effect of voltage andcurrent, thus forming a bridge 105 between the electrodes 102 and 103.Consequently, resistance between the electrodes 102 and 103 decreases.

[0131] On the contrary, when a proper positive voltage is applied to thesecond electrode 103, the mobile ions (atoms) 104 are dissolved into theelectronic/ionic mixed conductive material, resulting in thedisappearance of the bridge 105. In other words, the resistanceincreases. Hereinbelow, such a two-terminal device will be called an“atomic switch”. Japanese Patent Application No. 2000-265344, by theinventors of the present application, proposes the detailed principle ofoperation thereof.

[0132] A voltage VH/2 corresponding to a high-level output is applied tothe second electrode 103 of the atomic switch through a resistor 106(resistance R1). An input terminal V_(in) is connected to the secondelectrode 103 through a capacitor 108 (capacitance C1). On the otherhand, a voltage VL corresponding to a low-level output is applied to theconductive substance 101 functioning as the first electrode 102 of theatomic switch through a resistor 107 (resistance R2). An output terminalV_(out) is connected to the conductive substance 101.

[0133] It is assumed that R(ON) denotes a resistance of the atomicswitch in the ON state and R(OFF) denotes a resistance thereof in theOFF state. According to the present invention, the resistors and theatomic switch which satisfy the following relation are used.

R(OFF)>>R2>>R(ON)˜R1

[0134] For the input V_(in), VH is used as a high-level input and VL isused as a low-level input. When the input V_(in) is VL, the outputV_(out) indicates VH/2. When the input V_(in) is VH, the output V_(out)indicates VL. In other words, when the input is at a high level, theoutput goes to a low level. When the input is at a low level, the outputgoes to a high level. Thus, the atomic switch functions as a NOTcircuit.

[0135] Hereinbelow, an embodiment using an atomic switch, in which Ag₂Sformed on Ag is used as the first electrode 102 and Pt is used as thesecond electrode 103, will now be described. It is needless to say thata NOT circuit can be formed using an atomic switch having anotherelectronic/ionic mixed conductor such as Ag₂Se, Cu₂S, or Cu₂Se and ametal other than Pt.

[0136] As mentioned above, according to the present invention, the useof the atomic switch, serving as a two-terminal device comprising thefirst electrode 102 made of an electronic/ionic mixed conductivematerial and the second electrode 103 made of a conductive substance,realizes a NOT circuit comprising only the two-terminal devices.

[0137] In this instance, the case where VH is used as the high-levelinput V_(in) and VL (0 V) is used as the low-level input will be used asan example and the principle of operation of the NOT circuit shown inFIG. 14 will now be described in detail with reference to FIG. 15.

[0138] When the input V_(in) changes from a low level (VL) to a highlevel (VH) at time t1 [refer to FIG. 15(a)], charges Q=C1×VH (C1 denotesthe capacitance of the capacitor) are accumulated in the capacitor 108.At this time, a potential V_(in)′ of the second electrode 103 of theatomic switch changes due to a current, which temporarily flows, asshown in FIG. 15(b). In other words, the potential of the secondelectrode 103 of the atomic switch is temporarily higher than that ofthe first electrode 102, so that the atomic switch changes to the OFFstate (high resistance) [refer to FIG. 15(c)]. Thus, R(OFF)>>R2. Theoutput V_(out) indicates VL [refer to FIG. 15(d)].

[0139] Since the resistance of the atomic switch is increased, thepotential between the electrodes 102 and 103 of the atomic switch isincreased as shown in FIG. 15(e). Switching time ts is almost determinedby the capacitance C1 of the capacitor 108 and the resistance R1 of theresistor 106. For instance, when it is assumed that the capacitance C1of the capacitor is 1 pF and the resistance R1 is 10Ω, switching can beperformed on the order of gigahertzs.

[0140] On the other hand, when the input V_(in) changes from the highlevel (VH) to the low level (VL) at time t2 [refer to FIG. 15(a)], thecharges accumulated in the capacitor 108 are discharged. Due to acurrent which temporarily flows, the potential V_(in)′ of the secondelectrode 103 of the atomic switch changes as shown in FIG. 15(b). Inother words, the potential of the second electrode 103 in the atomicswitch is temporarily remarkably lower than that of the first electrode102, so that the atomic switch changes to the ON state (low resistance)[refer to FIG. 15(c)]. Consequently, R2>>R(ON). The output V_(out)indicates VH/2 [refer to FIG. 15(d)].

[0141]FIG. 15(e) shows the potential difference between the electrodes102 and 103 of the atomic switch. When the input V_(in) is at the lowlevel (VL), the potential difference between the electrodes 102 and 103of the atomic switch indicates about zero. Thus, the ON state of theatomic switch is held stably. On the other hand, when the input V_(in)is at the high level (VH), the potential difference between theelectrodes 102 and 103 of the atomic switch indicates VH/2. This valueindicates the potential difference at which the atomic switch should bein the OFF state. Therefore, the OFF state is held stably. In otherwords, the NOT circuit according to the present embodiment operates withreliability and stability.

[0142] According to the present embodiment, the case where VH or VL isused as an input and VH/2 or VL is used as an output is described. Inthe NOT circuit shown in FIG. 14, according to the principle ofoperation of the atomic switch, under limitations that a potentialdifference between inputs (in the present embodiment, VH−VL) has toalways be larger than a potential difference between outputs (in thepresent embodiment, VH/2−VL), the potential difference between inputsand that between outputs can be freely set within the limitations.

[0143] In the eleventh and twelfth embodiments, a case where thepotential difference between inputs is equivalent to that betweenoutputs will be described in detail. In other words, according to thepresent invention, a NOT circuit in which the level of an input isequivalent to the level of an output can be formed.

[0144]FIG. 16 is a schematic diagram of a NOT circuit according to atenth embodiment of the present invention.

[0145] A NOT circuit comprising two-terminal devices with arrangementdifferent from that shown in FIG. 14 will now be described as anotherembodiment.

[0146] The used components are exactly the same as those shown in FIG.14 according to the ninth embodiment. In other words, a first electrode112 serving as an electronic/ionic mixed conductor (Ag₂S) is formed onAg 111 serving as a conductive substance. Mobile ions (Ag ions) 114 inthe electronic/ionic mixed conductor are precipitated to form a bridge115 comprising Ag atoms between the first electrode 112 and a secondelectrode (Pt) 113. An atomic switch with the above structure is used.

[0147] A voltage VH/2 corresponding to a high-level output is applied tothe second electrode (Pt) 113 of the atomic switch through a resistor116 (resistance R3). An output terminal V_(out) is connected to thesecond electrode 113.

[0148] On the other hand, a voltage VL corresponding to a low-leveloutput is applied to the conductive substance (Ag) 111 constituting thefirst electrode 112 of the atomic switch through a resistor 117(resistance R4). An input terminal V_(in) is connected to the firstelectrode 112 through a capacitor 118 (capacitance C2).

[0149] It is assumed that R(ON) denotes a resistance of the atomicswitch in the ON state and R(OFF) denotes a resistance of the atomicswitch in the OFF state. According to the present embodiment, theresistors and the atomic switch, which satisfy the following relation,are used.

R(OFF)>>R3>>R(ON)˜R4

[0150] The principle of operation of the NOT circuit shown in FIG. 16will now be described in detail with reference to FIG. 17.

[0151] When the input V_(in) changes from a low level (VL) to a highlevel (VH) at time t1 [refer to FIG. 17(a)], charges Q=C2×VH (C2 denotesa capacitance of the capacitor) are accumulated in the capacitor 118. Atthis time, a potential V_(in)′ of the first electrode 112 in the atomicswitch changes due to a current, which temporarily flows, as shown inFIG. 17(b). In other words, the potential of the first electrode 112 inthe atomic switch is temporarily remarkably higher than that of thesecond electrode 113, so that the atomic switch changes to the ON state(low resistance) [refer to FIG. 17(c)].

[0152] Thus, R3>>R(ON). The output V_(out) indicates VL [refer to FIG.17(d)]. Switching time ts is almost determined by the capacitance C2 ofthe capacitor 118 and the resistance R4 of the resistor 117. Forinstance, when it is assumed that the capacitance C2 of the capacitor is1 pF and the resistance R4 is 10Ω, switching can be performed on theorder of gigahertzs.

[0153] On the other hand, when the input V_(in) changes from the highlevel (VH) to the low level (VL) at time t2 [refer to FIG. 17(a)], thecharges accumulated in the capacitor 118 are discharged. Due to acurrent which temporarily flows, the potential V_(in)′ of the firstelectrode 112 in the atomic switch changes as shown in FIG. 17(b). Inother words, the potential of the first electrode 112 in the atomicswitch is temporarily remarkably lower than that of the second electrode113, so that the atomic switch changes to the OFF state (highresistance) [refer to FIG. 17(c)]. Consequently, R(OFF)>>R3. The outputV_(out) indicates VH/2 [refer to FIG. 17(d)].

[0154]FIG. 17(e) shows the potential difference between the electrodes112 and 113 of the atomic switch. When the input V_(in) is at the lowlevel (VL), the potential difference between the electrodes 112 and 113of the atomic switch indicates VH/2. This value indicates a potentialdifference at which the atomic switch should be in the OFF state.Therefore, the OFF state is held stably.

[0155] On the other hand, when the input V_(in) is at the high level(VH), the potential difference between the two electrodes 112 and 113 ofthe atomic switch indicates substantially zero. Thus, the ON state ofthe atomic switch is held stably. In other words, the NOT circuitaccording to the present embodiment operates with reliability andstability.

[0156] According to the embodiment, the case where VH and VL are used asinputs and VH/2 and VL are used as outputs is described. In the samecase as the NOT circuit according to the ninth embodiment (FIG. 14),under limitations that a potential difference between inputs has toalways be larger than a potential difference between outputs, thepotential difference between inputs and that between outputs can befreely set within the limitations.

[0157] For the arrangement of the atomic switch, the resistors, and thecapacitor, and the number of each device, the pattern other than that ofthe above-mentioned embodiment can be made. The principalcharacteristics of the present invention are to use the above devices ascomponents.

[0158]FIG. 18 is a schematic diagram of a NOT circuit according to theeleventh embodiment of the present invention. FIG. 19 includes graphsshowing the principle of operation of the NOT circuit shown in FIG. 18.

[0159] The NOT circuit in which a potential difference between inputs isequivalent to that between outputs will now be described. A diode 109 isconnected to a portion (V_(out)′ in FIG. 18) corresponding to the outputof the NOT circuit according to the ninth embodiment (FIG. 14). VH isapplied to the other end of the diode 109 through a resistor 110(resistance R5). An output terminal V_(out) is connected to the otherend thereof. Further, the present NOT circuit differs from the NOTcircuit according to the ninth embodiment (FIG. 14) with respect to apoint that a voltage to be applied through the resistor 107 (resistanceR2) is not VL, but VS.

[0160] The potential of V_(out)′ is changed in the same way as the ninthembodiment except that the low level is not VL, but VS [refer to FIG.19(b)]. According to the present embodiment, by satisfying the relationof VH/2<VF(VH−VS) (VF denotes a threshold voltage of the diode 109), thepotential difference between inputs is equalized to that between outputsin the NOT circuit. In other words, when V_(out)′ indicates VH/2, avoltage that is equal to or lower than the threshold voltage is appliedto the diode 109. It is assumed that RB denotes a resistance of thediode 109 at this time and RF denotes a resistance thereof when avoltage that is equal to or higher than the threshold. The resistor 110which satisfies the relation of RB>>R5>>RF is used. FIG. 19(c) shows avoltage to be applied to the diode. The resistances and a voltage to beapplied are set so as to satisfy the following expressions.

R5/R2=(VH−VL)/(VL−VF−VS)

VL>VF+VS

[0161] Thus, the output V_(out) is changed as shown in FIG. 19(d). Inother words, the NOT circuit in which the potential difference betweeninputs is equivalent to that between outputs can be realized.

[0162]FIG. 20 is a schematic diagram of a NOT circuit according to atwelfth embodiment of the present invention.

[0163] A NOT circuit in which a potential difference between inputs isequivalent to that between outputs can be formed on the basis of the NOTcircuit according to the tenth embodiment shown in FIG. 16. A diode 119is connected to a portion (V_(out)′) corresponding to the output of theNOT circuit according to the tenth embodiment (FIG. 16). VH is appliedto the other end of the diode 119 through a resistor 120 (resistanceR6). An output terminal V_(out) is connected to the other end thereof.Further, the present NOT circuit differs from the NOT circuit accordingto the tenth embodiment with respect to a point that the voltage appliedthrough the resistor 117 (resistance R4) is not VL, but VS.

[0164] The principle of operation is substantially the same as that ofthe NOT circuit described in the eleventh embodiment. The resistor 120which satisfies the relation of RB>>R6>>RF is used and the resistancesand a voltage to be applied are set so as to satisfy the followingexpressions.

R 6/2R 4=(VH−VL)/(VL−VF−VS)

VL>VF+VS

[0165] On this condition, the NOT circuit in which the potentialdifference between inputs is equivalent to that between outputs can berealized. In the above case, the resistance of the atomic switch issubstantially equivalent to R4. When the condition does not apply, it isnecessary to control VS to some extent.

[0166] When the diode and the resistor are added to the NOT circuit inwhich the atomic switch, the resistors, and the capacitor are arrangedaccording to various patterns, the above-mentioned NOT circuit in whichthe potential difference between inputs is equivalent to that betweenoutputs can be constructed. In other words, the arrangement of theatomic switch, the resistors, the capacitor, and the diode is notlimited to that described in the present embodiment. The presentinvention is characterized in that these devices are used as components.

[0167]FIG. 21 is a schematic diagram of a one-digit binary adderaccording to a thirteenth embodiment of the present invention.

[0168] According to the present embodiment, a case where the one-digitbinary adder comprises a NOT circuit according to the present invention,an AND circuit, and an OR circuit, the AND circuit and the OR circuiteach having an atomic switch, will be described.

[0169] The NOT circuit according to the eleventh embodiment shown inFIG. 18 is used. The AND circuit and the OR circuit, proposed by theinventors of the present application in Japanese Patent Application No.2000-334686, are used. In the diagram, respective parts corresponding tothe NOT circuit, the AND circuit, and the OR circuit are surrounded bydotted lines. In other words, the present one-digit binary addercomprises two NOT circuits 121 and 122, three AND circuits 123, 124, and125, and one OR circuit 126.

[0170]FIG. 22 shows the circuits using logical symbols. In FIG. 22,reference numerals 121′ and 122′ denote the NOT circuits, 123′, 124′,and 125′ denote the AND circuits, and 126′ denotes the OR circuit.

[0171] For inputs X and Y, it is assumed that a high-level inputindicates 1 and a low-level input indicates 0. Outputs S and C are asshown in FIG. 23. According to the present invention, the one-digitbinary adder, which is applied to a computer, can be constructed. Thiscase is one example. According to the present invention, a NOT circuit,an AND circuit, and an OR circuit can be constructed using two-terminaldevices. Accordingly, all of logic circuits can be constructed usingonly the two-terminal devices.

[0172] The present invention is not limited to the above embodiments.Various modifications are possible on the basis of the spirit of thepresent invention and are not excluded from the scope of the presentinvention.

[0173] As mentioned above, according to the present invention, thefollowing advantages can be obtained.

[0174] (A) A high-speed point contact array with low power consumptioncan be constructed, resulting in the realization of a multiple recordingmemory device, a logic circuit, and an arithmetic circuit.

[0175] (B) Since a NOT circuit can be constructed using two-terminaldevices, all of logic circuits can be realized using only thetwo-terminal devices. A nanometer-sized atomic switch can be easilyformed. According to the present invention, therefore, a nanometer-scaledevice can be realized.

INDUSTRIAL APPLICABILITY

[0176] A point contact array, a NOT circuit, and an electronic circuitusing the same according to the present invention are applicable to alogic circuit, an arithmetic circuit, and a memory device which arenano-scale.

1. A point contact array comprising a plurality of electronic devices,each of which comprises a first electrode made of a compound conductivematerial having ionic conductivity and electronic conductivity and asecond electrode made of a conductive substance and each of which cancontrol conductance between the electrodes.
 2. The point contact arrayaccording to claim 1, wherein the compound conductive material havingmobile ions (M ion: M denotes a metallic atom) is formed on a source ofthe mobile ions (M).
 3. The point contact array according to claim 1 or2, wherein the compound conductive material is Ag₂S, Ag₂Se, Cu₂S, orCu₂Se.
 4. The point contact array according to claim 1, 2, or 3, whereinthe mobile ions, contained in the compound conductive material, form abridge between the first and second electrodes to change the conductancebetween the electrodes.
 5. The point contact array according to claim 1,2, or 3, wherein a semiconductor or insulator material, which candissolve ions and which exhibits electronic conductivity and ionicconductivity due to the dissolution of ions, is arranged between thefirst and second electrodes, and mobile ions contained in the compoundconductive material enter the semiconductor or insulator material tochange the conductance of the semiconductor or insulator.
 6. The pointcontact array according to claim 5, wherein the semiconductor orinsulator material is a crystal or an amorphous material of GeS_(x),GeSe_(x), GeTe_(x), or WO_(x) (0<x<100).
 7. The point contact arrayaccording to claim 1, 2, 3, 4, 5, or 6, wherein a metallic wire, ofwhich at least one part is covered with the compound conductivematerial, functions as the first electrode, a metallic wire functions asthe second electrode, a plurality of metallic wires functioning as atleast one of the electrodes exist, and a point contact is arranged ateach intersection of the metallic wires.
 8. The point contact arrayaccording to claim 1, 2, 3, 4, 5, 6, or 7, wherein the conductance ofeach point contact is quantized.
 9. The point contact array according toclaim 8, functioning as a multiple recording memory device in which thequantized conductance of each point contact is used as a recordingstate.
 10. The point contact array according to claim 8, wherein thequantized conductance of each point contact is used as an input signal,and the potentials of the respective electrodes are controlled toperform addition or subtraction of the input signals.
 11. The pointcontact array according to claim 1, 2, 3, 4, 5, 6, or 7, functioning asa logic circuit in which a potential at one end of each point contact isused as an input signal.
 12. (Deleted)
 13. A NOT circuit comprising anatomic switch serving as a two-terminal device.
 14. The NOT circuitaccording to claim 13, wherein the atomic switch comprises a device,which comprises a first electrode made of a compound conductive materialhaving ionic conductivity and electronic conductivity and a secondelectrode made of a conductive substance and which can controlconductance between the first and second electrodes.
 15. The NOT circuitaccording to claim 14, wherein the compound conductive material is Ag₂S,Ag₂Se, Cu₂S, or Cu₂Se.
 16. The NOT circuit according to claim 14 or 15,comprising a resistor and a capacitor, each of which serves as atwo-terminal device, in addition to the atomic switch.
 17. The NOTcircuit according to claim 16, comprising a diode in addition to theresistor and the capacitor.
 18. The NOT circuit according to claim 16,wherein a voltage to be applied to the atomic switch is controlledthrough the capacitor to control the conductance of the atomic switch.19. An electronic circuit comprising a combination of the NOT circuitaccording to any one of claims 13 to 18, and an AND circuit and an ORcircuit, each of which comprises the atomic switch.